• Course Code:  VA03

  • Term:  Summer 2015

  • Open for Enrollment

  • Self-paced

  • Course Author(s)
    Kunal Ghosh
Vlsi clock tree synthesis 2

VLSI Academy - Clock Tree Synthesis

Summer 2015

Computer Science

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    Kunal Ghosh
    Instructor

Course Summary

 

VLSI Academy - Clock Tree Synthesis

 

 

Clock Tree Networks are Pillars and Columns of a Chip.

 

With this series of lectures, we have explored on-site concepts applied in the VLSI industry. It is a One-Stop-Shop to understand Industrial VLSI circuits.

 

The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.

 

The goal of clock tree synthesis (CTS) is to minimize skew and insertion delay. Clock is not propagated before CTS as shown in the picture. After CTS, hold slack should improve. Clock tree begins at .sdc defined clock source, and ends at stop pins of flop. There are two types of stop pins known as ignore pins and sync pins. ‘Don’t touch’ circuits and pins in front end (logic synthesis) are treated as ‘ignore’ circuits or pins at back end (physical synthesis). ‘Ignore’ pins are ignored for timing analysis. If clock is divided, then separate skew analysis is necessary.

 

Global skew achieves zero skew between two synchronous pins without considering logic relationship.

 

Local skew achieves zero skew between two synchronous pins while considering logic relationship.

If clock is skewed intentionally to improve setup slack, then it is known as useful skew.

Rigidity is the term coined in Astro to indicate the relaxation of constraints. The higher the rigidity, the tighter the constraints.

 

 

Clock After CTS:

In clock tree optimization (CTO) clock can be shielded so that noise is not coupled to other signals. But shielding increases area by 12% to 15%. Since the clock signal is global in nature, the same metal layer used for power routing is used for clock also. CTO is achieved by buffer sizing, gate sizing, buffer relocation, level adjustment and HFN synthesis. We try to improve setup slack in pre-placement, in placement and post placement optimization before CTS stages, while neglecting hold slack. In post placement optimization after CTS, hold slack is improved. As a result of CTS, lots of buffers are added. Generally for 100k gates, around 650 buffers are added.

 

 

What are the requirements?

 Individuals must have basic knowledge of electrical subjects and electronics

 

 

What am I going to get from this course?

 CTS Quality Checks (Skew, Power, Latency, etc.)

 H-Tree

 Quality Check of H-Tree

 Clock Tree Buffering

 Buffered H-Tree

 H-Tree with uneven spread of Flops

 Advanced H-Tree for Million Flops

 Power Aware CTS (clock gating)

 Static Timing Analysis with Clock Tree

 

 

What is the target audience?

 Individuals who are keen to learn about VLSI and Chip World

 

 

Instructor Biography

 

 

Kunal Promode Ghosh, MTech, VLSI And Nano-Technology, IIT Mumbai

 

This course is a self initiative by Mr. Ghosh, an IIT Bombay Alumnus. He completed his Master's in VLSI and Nano-Technology from IIT Bombay, India.

He believes teaching is a nobel profession, so to keep the spirit burning, in association with this platform, he helps students understand the concepts of VLSI and Chip Design used in the semiconductor industry and professional world.

He has drilled down the huge concept into simple info-graphics and micro video formats, which are very easy to understand.

Hope you enjoy the session and Best of Luck for the future. 

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